Generally, a multi-port memory is used as a cache memory which functions as a memory common to the CPUs incorporated in a multi CPU system, or as an image memory in which the same address must be accessed at the same time. A plurality of word lines and a plurality of bit lines are connected to each memory cell of the multi-port memory. If data is written into any memory cell, while other data is being read from the same memory cell, the data read from the memory cell may not remain identical to the data stored in the cell before the reading of data. Hence, the processor or the like incorporated in the system usually reforms control, so that the data-writing and the data-reading may not conflict with each other.
In a system wherein data-writing and data-reading can be simultaneously performed on the same cell, any data is read from the cell after the data has been written into the cell, whereby the data remains identical. In this case, however, the read-access time increases. To avoid an increase in the read-access time, a method is employed in which the data to be read is bypassed to the bit line of a readout port or to the output of a sense amplifier.
FIG. 6 is a circuit diagram showing a conventional 2-port memory device.
Opposing data items are stored in a memory cell 602. One of the data items stored in the memory cell 602 are output to a bit line BLa via a transfer gate 603 in accordance with the potential of a word line WLa. The inverted data item stored in the memory cell 602 is output to a bit line /BLa through a transfer gate 605 in accordance with the potential of a word line WLa. In accordance with the potential of a word line WLb, the data stored in the memory cell 602 is output to a bit line BLb through a transfer gate 613 in accordance with the potential of a word line WLb, and the data inverted with respect to this data is transferred from the memory cell 602 to a bit line /BLb through a transfer gate 615.
Bit-line load circuits 617 and 627 designed for holding the potentials of the bit lines at power-supply potential V.sub.DD are connected between the bit lines BLa and /BLa and between the bit lines BLb and /BLb, respectively. More specifically, the current paths of the MOS transistors 618a and 618b forming the bit-line load circuit 617 are connected, at one end, to the bit lines BLa and /BLa and, at the other end, to the power-supply potential V.sub.DD. A write-enable signal /WEa is supplied to the gates of these MOS transistors 618a and 618b. The MOS transistors 628a and 628b constituting the bit-line load circuit 627 are connected, at one end, to the bit lines BLb and /BLb and, at the other end, to the power-supply potential V.sub.DD. A write-enable signal /WEb is supplied to the gates of these MOS transistors 628a and 628b.
Hereinafter, the input/output path using the bit lines BLa and /BLa shall be called "port a," and the input/output path using the bit lines BLb and /BLb shall be called "port b." When the write-enable signal /WEa for the port a is input to the gates of the MOS transistors 618a and 618b of the bit-line load circuit 617, and the port a is not used for writing data, the potentials of the bit lines BLa and /BLa are held at the power-supply potential V.sub.DD. Similarly, when the write-enable signal /WEb for the port b is input to the gates of the MOS transistors 628a and 628b of the bit-line load circuit 627, and the port b is not used for writing data, the potentials of the bit lines BLb and /BLb are held at the power-supply potential V.sub.DD.
The data-reading through the port a and the data-writing through the port b may conflict with each other, with respect to the memory cell 602. In this case, the bit-line load circuit 617 of the port a may delay the data-writing into the cell, or may render it impossible to write data thereinto at all. This is not only because the data the memory cell 602 latches is rewritten, but also because the data on the bit lines of the part a, i.e., the data-reading side at which the bit-line load circuit 617 remains on, is inverted. The more ports provided, the more prominent this problem is.
If data is read out after the delayed writing of the data described above, it is natural that much time is required to read the data. If no data can be written, it is can no longer be guaranteed that the data read out is identical to the data written.
As is shown in the figure, the memory cell 602 is an E/R-type cell which comprises an enhancement-type MOS transistor and a resistor. In the case where the memory cell is a full CMOS cell which comprises a CMOS only, the memory cell can hold data more stably than an E/R-type cell, and the problem described above is more acute.
FIG. 7 is a diagram explaining how the potentials of the bit lines BLa, /BLa, BLb, and /BLb change when the data-reading through the port a and the data-writing through the port b conflict with respect to the memory cell of the conventional memory device.
With reference to FIGS. 6 and 7, it will now be described how the potential of each bit line changes when the data-reading and the data-writing conflict with each other. Here it is assumed that, before time T.sub.0, the first memory node 650 connected to the transfer gates 605 and 515 of the memory cell 602 are at a low level "L," and the second memory node 660 connected to the transfer gates 603 and 613 are at a high level "H." Also, before time T.sub.0, the potential of each bit line is the difference between the power-supply potential V.sub.DD and the threshold voltage V.sub.th of the MOS transistors of the bit-line load circuit.
First, at time T.sub.0, the potentials of the word lines WLa and WLb rise, whereby the transfer gates are operated. Then, a current path is formed between the memory cell 602 and the bit lines BLa and /BLa, and a current path is formed between the memory cell 602 and the bit lines BLb and /BLb. The potentials of the bit lines /BLa and /BLb are thereby lowered to the low level, whereby a potential difference occurs between the bit lines BLa and BLb.
Next, at time T.sub.1, the write-enable signal /WEb falls, and the writing of data is started. Then, until the signal /WEb rises again, the bit-line load circuit 627 of the port b remains off. Thereafter, at time T.sub.2, the potential of the bit line BLb and that of the bit line /BLb are inverted due to the data-writing operation. Then, at time T.sub.3, the potential of the bit line BLa and that of the bit line /BLa are inverted. T.sub.3 -T.sub.1 =.tau.W, where .tau.W is the period between the rising of the write-enable signal /WEb and the completion of inversion of the bit-line potentials of both ports. In the circuit shown in FIG. 6, the reading of data is effected at the same time as the writing of data, and the bit lines of the port a, whose bit-line load circuit 617 is on, are driven Hence, the data-writing period .tau.W is long.